1. Field of the Invention
The present invention relates to a process of manufacturing a semiconductor device in which a highly integrated, microstructured CMOS transistor and a bipolar transistor having high driving and high speed performance are formed on a single semiconductor substrate. Particularly, the present invention relates to a process of manufacturing a Bi-CMOS device, utilizing a simple combination of a bipolar transistor manufacturing process and a MOS transistor manufacturing process.
2. Description of the Related Art
The more the CMOS transistor is miniaturized, the thinner the impurity diffusion regions constituting a source/drain regions become to suppress a short-channel effect. As a result, the sheet resistance of the source/drain regions increases and driving performance thereby deteriorates. To prevent this, a technique called a self-aligned silicide technique has been developed. The technique is to provide titanium silicide (TiSi), molybdenum silicide (MoSi), tungsten silicide (WSi) or the like on the source and drain in a self-aligned manner. To be more specific, a metal film made of, for example, Ti, Mo, W is formed on a semiconductor substrate and only a part of the metal film which is provided on the silicon layer on the semiconductor substrate is made into silicide.
Meanwhile, the growth speed of the titanium silicide or the like is slow on an N-type silicon and fast on a P-type silicon. Due to this, during an ordinary CMOS process, silicide formed on the source/drain regions of an NMOS transistor becomes thinner than that formed on the source/drain regions of a PMOS transistor. As the film is thinner, the sheet resistance of the titanium silicide increases and heat resistance thereof decreases, with the result that agglomeration tends to easily occur on the NMOS transistor at the time of heat treatment in the later step. On the other hand, if silicide is made thick, it is put close to the junction of the source/drain regions of the PMOS transistor and therefore junction leak tends to easily occur through the source/drain regions. The agglomeration of the silicide on the NMOS transistor and the junction leak on the source/drain regions of the PMOS transistor, thus, are in trade-off and affect the application of the self-aligned silicide technique to a CMOS transistor device.
To overcome the above-mentioned problem, a technique called a raised source and drain process or an elevated source and drain process has been developed. In this process, a silicon film having a low impurity concentration and a predetermined thickness has been previously deposited by epitaxy on source/drain regions so that only the film is used for silicide. Thereafter, self-aligned silicide process is carried out.
As mentioned above, if the elevated source and drain process is applied, only a silicon film formed on the source/drain regions in advance is used for the self-aligned silicide process and the source/drain regions are not influenced by the process, thereby preventing junction leak through the source/drain regions. According to the self-aligned silicide process utilizing the above technique, a series of steps of growing a silicon film by epitaxy, depositing metal thereon and silicifying the metal with the silicon are carried out to thereby form a silicide film in the final stage of the formation of a transistor. That is, after the formation of source/drain regions and a gate region, a silicide film is formed by a series of these steps.
If the CMOS transistor formed by the above process and a high speed bipolar transistor formed by a known double-layer polysilicon self-alignment process are fabricated on a single semiconductor substrate, short circuit tends to occur between a base electrode and an emitter electrode of the bipolar transistor. The reason is as follows. In a semiconductor device of this type, a silicon film is grown on the base electrode and the emitter electrode of a bipolar transistor by epitaxy before silicifying the surface regions of the electrodes with the silicon film. During the growth, short circuit tends to occur between the electrodes. This makes it necessary to separate the self-aligned silicide step of a CMOS transistor from that of a bipolar transistor, resulting in a lengthy process.
The present invention has been made to solve these disadvantages. Its object is to provide a process of manufacturing a semiconductor device utilizing a combination of a bipolar transistor manufacturing process and a MOS transistor manufacturing process wherein a silicide film is effectively formed on a semiconductor substrate having a CMOS transistor and a bipolar transistor formed thereon.